NAND Design Rule - Director

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Director - NAND EnRGe (Design Enablement. Design Rules and Generators)
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron has a unique opportunity for a highly experienced Design Rule leader to join our Advanced NAND Technology team. As Director - NAND EnRGe (Design Enablement. Design Rules and Generators) your primary leadership responsibility is to be a catalyst for next generation NAND design rule development! Responsibilities include but are not limited to: Lead worldwide EnRGe team to deliver high quality DR PDK and generator collateral and enable zero-error mask tape-outs Coordinate the work of engineers from multiple groups to develop Design Rules, Requirements, Test Structures and improve process margin for all NAND generations from early development until manufacturing ceases Pro-actively identify and address process issues and process windows stemming from database layout or layout techniques Partner with Design, Product Engineering, Process Integration, Business Units and Quality groups to optimize PPAC (Performance, Power, Area, Cost) for all Micron NAND products Assure that correct DRCs (Design Rule Checks) are in place Manage effort to build and evaluate test structures to provide data for next generation devices and quantify process margin on current devices Summarize sophisticated problems; drive action plan resolution taken based on findings Define and execute project plans including quarterly milestones and lead measures to achieve target deliverables and timelines Lead timely information exchange between Layout/Design, Process Integration, Product Engineering, and Advanced Mask teams Drive timely closure of open items through communication within PI/Layout/Design teams Manage reticle budgets across all NAND part types from pathfinding to HVM Build and maintain a culture of excellence and continual improvement Minimum Qualifications: MS/PhD in Electrical Engineering, Microelectronics, Physics or related field Demonstrated experience overseeing an engineering team (5+ direct reports) Senior level (10+ years) experience in semiconductor industry areas: Design Rules, Process Integration, Yield Enhancement, Product Engineering, Design, Test Structure Development, Unit Process Development Solid grasp and exposure to design layout; ability to do innovative floor plan/layout work Success resolving sophisticated technical issues and situations Ability to think and act dynamically and clearly in urgent or stressed situations Hands-on understanding of NAND process flow As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
Location:
Boise
Job Type:
FullTime

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