Director Design Verification Engineering page is loaded Director Design Verification Engineering Apply locations San Jose, California, United States time type Full time posted on Posted 2 Days Ago job requisition id R01019 Job Details: Job Description: Directs and manages a team of design verification engineers responsible for IP and SoC design verification.

Deploys and manages leading silicon design verification processes, procedures, verification tools, and technologies based on latest best industry practices.

Works with architecture, design, microarchitecture, software and post-silicon validation teams to identify design bugs and improve overall quality of the product.

Collaborates with program leaders to define verification plans, drive coverage closure and regression metrics against milestone requirements.

Drives verification methodologies and adoption including UVM, formal and emulation/prototyping to ensure industry best practices.

Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results.

Drives results by inspiring people, role modeling Altera values, developing the capabilities of others, and ensuring a productive work environment.

Lead, mentor and grow a high performance DV team, across multiple sites. Recruit and retain top DV talent and foster a culture of technical excellence and innovation.

Salary Range Our compensation reflects the cost of labor within the US market.Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $230.4k - $270.1k USD Qualifications: Bachelors degree in Electrical Engineering, Computer Engineering, or related field. 15+ years of experience in ASIC/SOC/FPGA verification, including 8+ years in a technical management of leadership role. Demonstrated experience of high quality tapeout of complex ASIC/SoC/FPGAs Demonstrated experience of DV flows and verification infrastructure Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Similar Jobs (5) Design Technology Co-Optimization (DTCO) Engineer / Circuit Design Engineer remote type In-Office locations 2 Locations time type Full time posted on Posted 3 Days Ago FPGA Silicon Design Engineer locations San Jose, California, United States time type Full time posted on Posted 30+ Days Ago SoC Logic Design Engineer locations 2 Locations time type Full time posted on Posted 30+ Days Ago Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Ourend-to-endbroad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet. Don't see the dream job you are looking for? Click " Get Started " below to drop off your contact information and resume and we will reach out to you if we find the perfect fit.

#J-18808-Ljbffr